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PRISM

Visibility and store buffers

advanced · commonly asked

Two threads write, then read each other. Under sequential consistency both reading zero is impossible; on real hardware it happens — and no interleaving explains it.

Enumerating the interleavings

What this shows

A write is not visible when it happens, it is visible when it is published. This is where the interleaving model runs out and a memory model is required.

Why it is asked

What `volatile` actually guarantees, and why it is about publication rather than atomicity. Most candidates have this exactly backwards.

In an interview

What `volatile` actually guarantees, and why it is about publication rather than atomicity. Most candidates have this exactly backwards.

  • memory model
  • volatile
  • store buffer
  • happens-before

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